library IEEE;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
USE ieee.numeric_std.all;

entity desplazador is
	port (
		  entrada		: IN		std_logic_vector(7 downto 0);
		  direccion		: IN		std_logic;
		  cantidad		: IN		integer;
		  salida		: OUT		std_logic_vector(7 downto 0)
		 );
end desplazador;

architecture arch_desplazador of desplazador is
	signal i : integer;
	signal j : integer;
begin
	process (direccion, cantidad, entrada)
	begin
		if(direccion = '0') then
			for i in 0 to 7 loop
				if(i <= 7-cantidad) then
					salida(i) <= entrada(i+cantidad);
				else
					salida(i) <= '0';
				end if;
			end loop;
		else
			for i in 7 downto 0 loop
				if (i >= cantidad) then
					salida(i) <= entrada(i-cantidad);
				else
					salida(i) <= '0';
				end if;
			end loop;
		end if;
	end process;
end arch_desplazador;